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etrontech em639325 etron technology, inc. no. 6, technology rd. v, hsinchu sci ence park, hsinchu, taiwan 30078, r.o.c. tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc. reserves the right to change products or specification without notice. 4m x 32 bit synchronous dram (sdram) advance (rev. 2.1, aug. /2015) features ? fast access time from clock: 5/5.4/5.4 ns ? fast clock rate: 200/166/143 mhz ? fully synchronous operation ? internal pipelined architecture ? four internal banks (1m x 32-bit x 4bank) ? programmable mode - cas latency: 2 or 3 - burst length: 1, 2, 4, 8, or full page - burst type: sequential & interleaved - burst-read-single-write ? burst stop function ? individual byte controlled by dqm0-3 ? auto refresh and self refresh ? 4096 refresh cycles/64ms ? single 3.3v 0.3v power supply ? industrial temperature: t a = -40~85 c ? interface: lvttl ? 86-pin 400 mil plastic tsop ii package - pb free and halogen free ? 90-ball 8 x 13 x 1.2mm fbga package - pb and halogen free overview the em639325 sdram is a high-speed cmos synchronous dram contai ning 128 mbits. it is internally configured as a quad 1m x 32 dram with a synchronous interface (a ll signals are registered on the positive edge of the clock signal, clk). each of the 1m x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bankactivate command which is then followed by a read or write command. the em639325 provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiat ed at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth. table 1. key specifications em639325 -5i/6i/7i tck3 clock cycle time(min.) 5/6/7 ns tac3 access time from clk (max.) 5/5.4/5.4 ns tras row active time(min.) 40/42/42 ns trc row cycle time(min.) 55/60/63 ns table 2. ordering information part number frequency package EM639325TS-5IG 200mhz tsop ii em639325ts-6ig 166mhz tsop ii em639325ts-7ig 143mhz tsop ii em639325bk-5ih 200mhz fbga em639325bk-6ih 166mhz fbga em639325bk-7ih 143mhz fbga ts: indicates tsop ii package bk: indicates 8 x 13 x 1.2mm fbga package i: indicates industrial grade g: indicates pb and halogen free for tsop ii package h: indicates pb and halogen free for fbga package
etrontech em639325 rev. 2.1 2 aug. /2015 figure 1. pin assignment (top view) 186 vdd vss 285 dq0 dq15 384 vddq vssq 483 dq1 dq14 582 dq2 dq13 681 vssq vddq 780 dq3 dq12 879 dq4 dq11 978 vddq vssq 10 77 dq5 dq10 11 76 dq6 dq9 12 75 vssq vddq 13 74 dq7 dq8 14 73 nc nc 15 72 vdd vss 16 71 dqm0 dqm1 18 69 cas# nc 19 68 ras# clk 20 67 cs# cke 22 65 ba0 a8 23 64 ba1 a7 24 63 a10/ap a6 25 62 a0 a5 26 61 a1 a4 27 60 a2 a3 28 59 dqm2 dqm3 29 58 vdd vss 17 70 we# nc 21 66 a11 a9 31 56 dq16 dq31 32 55 vssq vddq 33 54 dq17 dq30 34 53 dq18 dq29 35 52 vddq vssq 36 51 dq19 dq28 37 50 dq20 dq27 38 49 vssq vddq 30 57 nc nc 39 48 dq21 dq26 40 47 dq22 dq25 41 46 vddq vssq 42 45 dq23 dq24 43 44 vdd vss
etrontech em639325 rev. 2.1 3 aug. /2015 figure 2. ball assignment (top view) vddq dq31 dq28 dq27 dq23 dq24 dq16 a b c d e 123 789 dq26 vddq vssq vssq dq29 vddq vss vssq dq25 dq30 nc vdd vssq dq22 dq20 dq17 dq18 nc dq21 dq19 vddq vddq vssq f vss dqm3 a3 a2 dqm2 vdd g a4 a5 a6 a10 a0 a1 h a7 a8 nc nc ba1 a11 j clk cke a9 ba0 cs# ras# k dqm1 nc nc cas# we# dqm0 l vddq dq8 vss vdd dq7 vssq m vssq dq10 dq9 dq6 dq5 vddq n vssq dq12 dq14 dq1 dq3 vddq p dq11 vddq vssq vddq vssq dq4 r dq13 dq15 vss vdd dq0 dq2
etrontech em639325 rev. 2.1 4 aug. /2015 figure 3. block diagram clk cke cs# ras# cas# we# clock buffer command decoder column counter control signal generator address buffer refresh counter dq buffer 4096 x 256 x 32 cell array (bank #0) row decoder 4096 x 256 x 32 cell array (bank #1) row decoder 4096 x256 x 32 cell array (bank #2) row decoder 4096 x 256 x 32 cell array (bank #3) row decoder column decoder column decoder column decoder column decoder mode register a9 a11 ba0 ba1 ~ a0 dq31 dq0 ~ dqm0~3 a10/ap
etrontech em639325 rev. 2.1 5 aug. /2015 pin descriptions table 3. pin details symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also incr ements the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivates (low) the clk signal. if cke goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and t he state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. cke is synchronous exc ept after the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the input buffers, including clk, are disabled during power down and self refresh modes, providi ng low standby power. ba0, ba1 input bank activate: ba0 and ba1 defines to which bank the bankactivate, read, write, or bankprecharge command is being applied. the bank address ba0 and ba1 is used latched in mode register set. a0-a11 input address inputs: a0-a11 are sampled during the bankactivate command (row address a0-a11) and read/write command (column address a0- a 7 with a10 defining auto precharge) to select one location out of the 1m available in the respective bank. during a precharge command, a10 is sampled to determine if all banks are to be precharged (a10 = high). th e address inputs also provide the op- code during a mode register set or special mode register set command. cs# input chip select: cs# enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank selection on system s with multiple banks . it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signal s and is latched at the positive edges of clk. when ras# and cs# are asserted "low" and cas# is asserted "high," either the bankactivate command or the precharge command is selected by the we# signal. when the we# is asserted "high," the bankactivate command is selected and the bank designated by ba is turn ed on to the active state. when the we# is asserted "low," the precharge command is selected and the bank designated by ba is switched to the idle state after the pr echarge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signal s and is latched at the positive edges of clk. when ras# is held "high" and cs# is asserted "low," the column access is started by asserting cas# "low." then, the read or write command is selected by asserting we# "low" or "high." we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at the positive edges of clk. the we# input is used to select the bankactivate or precharge command and read or write command. dqm0- dqm3 input data input/output mask: data input mask: dqm0-dqm3 are byte specific. input data is masked when dqm is sampled high during a write cycle. dqm3 masks dq31-dq24, dqm2 masks dq23-dq16, dqm1 masks dq15-dq8, and dqm0 masks dq7-dq0. dq0- dq31 input/ output data i/o: the dq0-31 input and output data are synchronized with the positive edges of clk. the i/os are byte-maskable during reads and writes.
etrontech em639325 rev. 2.1 6 aug. /2015 nc - no connect: these pins should be left unconnected. v ddq supply dq power: provide isolated power to dqs for improved noise immunity. v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v dd supply power supply: 3.3v ? 0.3v. v ss supply ground
etrontech em639325 rev. 2.1 7 aug. /2015 operation mode fully synchronous operations are performed to latc h the commands at the positive edges of clk. table 4 shows the truth table for the operation commands. table 4. truth table (note (1), (2)) command state cke n-1 cke n dqm (6) ba 0,1 a 10 a 11 , a 9-0 cs# ras# cas# we# bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x v v l l h l l write and autoprecharge active (3) h x v v h column address (a0 ~ a7) l h l l read active (3) h x v v l l h l h read and autoprecharge active (3) h x v v h column address (a0 ~ a7) l h l h mode register set idle h x x op code l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x h x x x l v v v power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x note: 1. v = valid, x = don't care, l = logic low, h = logic high 2. cke n signal is input level when commands are provided. cke n-1 signal is input level one clock cy cle before the commands are provided. 3. these are states of bank designated by ba signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle, device state is clock suspend mode. 6. dqm0-3
etrontech em639325 rev. 2.1 8 aug. /2015 commands 1 bankactivate (ras# = "l", cas# = "h", we# = "h", ba 0,1= bank, a0-a11 = row address) the bankactivate command activates the idle bank designated by the ba0,1 (bank activate) signal. by latching the row address on a0 to a1 1 at the time of this command, the selected row access is initiated. the read or write operation in the same bank can occur after a time delay of t rcd (min.) from the time of bank activation. a s ubsequent bankactivate command to a different row in the same bank can only be issued after the prev ious active row has been precharged (refer to the following figure). the minimum time interval between successive bankactivate commands to the same bank is defined by t rc (min.). the sdram has four internal banks on the same chip and shares part of the internal circuitry to r educe chip area; therefore it restri cts the back-to-back activation of the two banks. t rrd (min.) specifies the minimum time required between activating different banks. after this command is used, the write command performs the no mask write operation. figure 4. bankactivate command cycle (burst length = n) clk command t0 t1 address t2 t3 tn+3 tn+4 tn+5 tn+6 ras# - cas# delay(t rcd ) ras# - ras# delay time(t rrd ) ras# - cycle time(t rc ) autoprecharge begin bank a row addr. bank a col addr. bank b row addr. bank a row addr. bank a activate nop nop r/w a with autoprecharge bank b activate nop nop bank a activate don?t care 2 bankprecharge command (ras# = "l", cas# = "h", we# = "l", ba0, 1 = bank, a10 = "l", a0-a9, a11 = don't care) the bankprecharge command precharges the bank designated by ba0, 1 signal. the precharged bank is switched from the active state to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in the desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge function must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 prechargeall command (ras# = "l", cas# = "h", we# = "l", ba0,1 = do n?t care, a10 = "h", a0-a9, a11 = don't care) the prechargeall command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. all banks are then switched to the idle state. 4 read command (ras# = "h", cas# = "l", we# = "h", ba0, 1 = bank, a10 = "l", a0-a7 = column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the read command is issued. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the iss ue of the read command. each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). the dqs go into high-impedance at the end of the burst unless ot her command is initiated. the burst length, burst sequence, and cas latency are determined by the mode register which is already programmed. a full-page burst will continue until terminated (at t he end of the page it will wrap to column 0 and continue).
etrontech em639325 rev. 2.1 9 aug. /2015 figure 5. burst read operation (burst length = 4, cas# latency = 2, 3) clk t0 t1 command t2 t3 t4 t5 t6 t7 t8 cas# latency=2 t ck2, dq cas# latency=3 t ck3, dq read a nop nop nop nop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 the read data appears on the dqs subject to the va lues on the dqm inputs two clocks earlier (i.e. dqm latency is two clocks for output buffers). a r ead burst without the auto precharge function may be interrupted by a subsequent read or write comm and to the same bank or the other active bank before the end of the burst lengt h. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the read command can occur on any clock cycle following a previous read command (refer to the following figure). figure 6. read interrupted by a read (burst length = 4, cas# latency = 2, 3) clk t0 t1 command t2 t3 t4 t5 t6 t7 t8 cas# latency=2 t ck2, dq cas# latency=3 t ck3, dq read a read b nop nop nop nop nop nop nop dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 the dqm inputs are used to avoid i/o contention on the dq pins when the interrupt comes from a write command. the dqms must be asserted (hig h) at least two clocks prior to the write command to suppress data-out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with high-impedance on the dq pins must occur between the last read data and the write command (refer to the following figure). if the data output of the bur st read occurs at the second clock of the burst write, the dqms must be asserted (high) at least one clock prior to the write command to avoid internal bus contention.
etrontech em639325 rev. 2.1 10 aug. /2015 figure 7. read to write interval (burst length 4, cas# latency = 2) clk command t0 t1 dqm t2 t3 t4 t5 t6 t7 t8 cas# latency=2 t ck2, dq must be hi-z before the write command nop nop banka activate nop read a write a din a 0 din a 1 nop nop din a 2 nop t9 din a 3 nop figure 8. read to write interval (burst length 4, cas# latency = 2) don?t care clk command t0 t1 dqm t2 t3 t4 t5 t6 t7 t8 cas# latency=2 t ck2, dq must be hi-z before the write command nop read a nop nop nop din b 3 din b 2 din b 1 din b 0 nop write b nop nop figure 9. read to write interval (burst length 4, cas# latency = 3) clk command t0 t1 t2 t3 t4 t5 t6 nop read a nop nop nop nop write b nop t7 t8 nop dqm dout a 0 din b 0 din b 1 din b 2 cas# latency=3 t ck3 , dq must be hi-z before the write command don?t care a read burst without the auto precharge func tion may be interrupted by a bankprecharge/ prechargeall command to the same bank. the following figure shows the optimum time that bankprecharge/ prechargeall command is issued in different cas latency.
etrontech em639325 rev. 2.1 11 aug. /2015 figure 10. read to precharge (cas# latency = 2, 3) clk t0 t1 address t2 t3 t4 t5 t6 t7 t8 cas# latency=2 t ck2, dq cas# latency=3 t ck3, dq command trp nop nop precharge nop bank(s) nop nop read a bank, col a dout a 0 dout a 1 dout a 3 dout a 2 dout a 2 dout a 1 dout a 0 dout a 3 bank row activate nop don?t care 5 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", ba = bank, a10 = "h", a0-a7 = column address) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this command is given, any subsequent command cannot occur within a time delay of {t rp (min.) + burst length}. at full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. 6 write command (ras# = "h", cas# = "l", we# = "l", ba = bank, a10 = "l", a0-a7 = column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be regist ered on each successive positive clock edge (refer to the following figure). the dqs remain with high-impedance at the end of the burst unless another command is initiated. the burst length and burst sequence are determined by the mode register, which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). figure 11. burst write operation (burst length = 4) clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 din a 2 din a 3 t7 t8 command nop write a nop nop nop nop nop nop nop the first data element and the write are registered on the same clock edge don?t care a write burst without the autoprecharge func tion may be interrupted by a subsequent write, bankprecharge/prechargeall, or read command befo re the end of the burst length. an interrupt coming from write command can occur on any cl ock cycle following the previous write command (refer to the following figure).
etrontech em639325 rev. 2.1 12 aug. /2015 figure 12. write inte rrupted by a write (burst length = 4) clk t0 t1 command t2 t3 t4 t5 t6 t7 t8 dq nop write a write b nop nop nop nop nop nop din a 0 din b 0 din b 1 din b 2 din b 3 the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is regist ered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read command is registered, the data inputs will be igno red and writes will not be executed. figure 13. write inte rrupted by a read (burst length = 4, cas# latency = 2, 3) don?t care clk t0 t1 command t2 t3 t4 t5 t6 t7 t8 cas# latency=2 t ck2, dq cas# latency=3 t ck3, dq input data must be removed from the dq at least one clock cycle before the read data appears on the outputs to avoid data contention nop write a read b nop nop nop nop nop nop din a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout b 3 dout b 2 dout b 1 dout b 0 din a 0 the bankprecharge/prechargeall command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, starti ng with the clock edge following the last data-in element and ending with the clock edge on wh ich the bankprecharge/prechargeall command is entered (refer to the following figure).
etrontech em639325 rev. 2.1 13 aug. /2015 figure 14. write to precharge don?t care clk t0 t1 address t2 t3 t4 t5 command trp dqm dq twr write precharge nop nop activate nop bank col n bank(s) row din n din n+1 nop nop t6 t7 note: the dqms can remain low in this example if the length of the write burst is 1 or 2. 7 write and autoprecharge command (ras# = "h", cas# = "l", we# = "l", ba = bank, a10 = "h", a0-a7 = column address) the write and autoprecharge command performs the precharge operation automatically after the write operation. once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + t wr + t rp (min.)}. at full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. figure 15. burst write with auto-precharge (burst length = 2) clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 t7 t8 command bank a activate nop nop write a auto precharge nop nop nop nop nop t9 bank a activate t dal =t wr +t rp t dal begin autoprecharge bank can be reactivated at completion of t dal 8 mode register set command (ras# = "l", cas# = "l", we# = "l", a0-a11 = register data) the mode register stores the data for controlli ng the various operating modes of sdram. the mode register set command programs the values of cas latency, addressing mode and burst length in the mode register to make sdram useful for a variety of different applications. the default values of the mode register after power-up are undefined; therefore this command must be issued at the power-up sequence. the state of pins a0~a9 and a11 in the sa me cycle is the data written to the mode register. two clock cycles are required to co mplete the write in the mode register (refer to the following figure). the contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state.
etrontech em639325 rev. 2.1 14 aug. /2015 table 5. mode register bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 w.b.l tm cas latency bt burst length a9 write burst length a8 a7 test mode a3 burst type 0 burst 0 0 normal 0 sequential 1 single bit 1 0 reserved 1 interleave 0 1 reserved a6 a5 a4 cas latency a2 a1 a0 burst length 0 0 0 reserved 0 0 0 1 0 0 1 reserved 0 0 1 2 0 1 0 2 clocks 0 1 0 4 0 1 1 3 clocks 0 1 1 8 1 0 0 reserved 1 1 1 full page (sequential) all other reserved all other reserved note: column address is repeated until terminated in full page mode figure 16. mode re gister set cycle clk cs# t0 t1 t2 t3 t4 t5 t6 t7 cke don?t care ras# t mrd cas# t8 t9 t10 we# ba0,1 a10 a0-a9, a11 dqm dq t rp prechargeall mode register set command any command hi-z address key
etrontech em639325 rev. 2.1 15 aug. /2015 ? burst definition, addressing sequence of sequential and interleave mode table 6. burst definition start address burst length a2 a1 a0 sequential interleave x x 0 0, 1 0, 1 2 x x 1 1, 0 1, 0 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 4 x 1 1 3, 0, 1, 2 3, 2, 1, 0 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page location = 0-255 n, n+1, n+2, n+3, ?255, 0, 1, 2, ? n-1, n, ? not support 9 no-operation command (ras# = "h ", cas# = "h", we# = "h") the no-operation command is used to perform a no p to the sdram which is selected (cs# is low). this prevents unwanted commands from bein g registered during idle or wait states. 10 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate ei ther fixed-length or full-page bursts. this command is only effective in a read/write burst wi thout the auto precharge function. the terminated read burst ends after a delay equal to the cas latency (refer to the following figure). the termination of a write burst is shown in the following figure. figure 17. termination of a burst read operation (burst length 4, cas# latency = 2, 3) clk t0 t1 command t2 t3 t4 t5 t6 t7 t8 cas# latency=2 t ck2, dq cas# latency=3 t ck3, dq the burst ends after a delay equal to the cas# latency nop nop read a dout a 0 dout a 0 dout a 1 nop dout a 1 dout a 2 burst stop nop dout a 3 dout a 2 nop dout a 3 nop nop
etrontech em639325 rev. 2.1 16 aug. /2015 figure 18. termination of a burst write operation (burst length = x) don?t care clk dq t0 t1 command t2 t3 t4 t5 t6 t7 t8 nop write a din a 0 nop din a 1 nop din a 2 burst stop nop nop nop nop 11 device deselect command (cs# = "h") the device deselect command disables the command decoder so that the ras#, cas#, we# and address inputs are igno red, regardless of whether the clk is enabled. this command is similar to the no operation command. 12 autorefresh command (ras# = "l", cas# = "l", we# = "h",cke = "h", ba0,1 = ?don?t care, a0-a11 = don't care) the autorefresh command is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventiona l drams. this command is non-persistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don't care" during an autorefresh command. the internal refresh counter increments automatically on every au to refresh cycle to all of the rows. the refresh operation must be performed 4096 times within 64ms. the time required to complete the auto refresh operation is specified by t rc (min.). to provide the autorefresh command, all banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be followed by nops until the auto refresh operation is completed. the precharge time requirement, t rp (min), must be met before successive auto refresh operations are performed. 13 selfrefresh entry command (ras# = "l", cas# = "l", we# = "h", cke = "l", a0-a11 = don't care) the selfrefresh is another refresh mode avail able in the sdram. it is the preferred refresh mode for data retention and low power operation. on ce the selfrefresh command is registered, all the inputs to the sdram become "don't care" with the exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power consumption. the sdram may remain in selfrefresh mode for an indef inite period. the selfrefresh mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 14 selfrefresh exit command (cke = "h", cs# = "h" or cke = "h", r as# = "h", cas# = "h", we# = "h") this command is used to exit from the selfrefr esh mode. once this command is registered, nop or device deselect commands must be issued for t rc (min.) because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cy cles should be completed just prior to entering and just after exiting the selfrefresh mode. 15 clock suspend mode entry / powerdown mode entry command (cke = "l") when the sdram is operating the burst cycle, th e internal clk is suspended (masked) from the subsequent cycle by issuing this command (ass erting cke "low"). the device operation is held intact while clk is suspended. on the other hand, when all banks are in the idle state, this command performs entry into the powerdown mode. all i nput and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh pe riod (64ms) since the command does not perform any refresh operations.
etrontech em639325 rev. 2.1 17 aug. /2015 16 clock suspend mode exit / powerdown mode exit command when the internal clk has been suspended, the operation of the internal clk is reinitiated from the subsequent cycle by providing this command (asserting cke "high", the command should be nop or deselect). when the device is in the po werdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t xsr (min.) is required when the device exits from the powerdown mode. any subsequent commands can be issued after one clock cycle from the end of this command. 17 data write / output enable, data mask / output disable command (dqm = "l", "h") during a write cycle, the dqm signal functions as a data mask and can control every word of the input data. during a read cycle, the dqm functions as the controller of output buffers. dqm is also used for device selection, byte select ion and bus control in a memory system.
etrontech em639325 rev. 2.1 18 aug. /2015 table 7. absolute maximum rating symbol item values unit note v in , v out input, output voltage -1.0 ~ 4.6 v v dd , v ddq power supply voltage -1.0 ~ 4.6 v t a ambient temperature -40 ~ 85 c t stg storage temperature -55 ~ 150 c p d power dissipation 1.1 w i os short circuit output current 50 ma note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. table 8. recommended d.c. operating conditions (v dd = 3.3v ? 0.3v, t a = -40~85c) symbol parameter/ condition min. typ. max. unit note v dd dram core supply voltage 3.0 3.3 3.6 v 2 v ddq i/o supply voltage 3.0 3.3 3.6 v 2 v ih input high level voltage 2 - v ddq +0.3 v 2 v il input low level voltage -0.3 - 0.8 v 2 i il input leakage current ( 0v vin vdd, all other pins not under test = 0v ) -10 - 10 a i oz output leakage current (output disable, 0v vin vddq ) -10 - 10 a v oh output high level voltage ( i out = -2ma ) 2.4 - - v v ol output low level voltage ( i out = 2ma ) - - 0.4 v table 9. capacitance (v dd = 3.3v, f = 1mhz, t a = 25c) symbol parameter min. max. unit c i input capacitance 3.5 5.5 pf c i/o input/output capacitance 5.5 7.5 pf note: these parameters are periodically sampled and are not 100% tested.
etrontech em639325 rev. 2.1 19 aug. /2015 table 10. d.c. characteristics (v dd = 3.3v ? 0.3v, t a = -40~85c) -5i -6i -7i description/test condition symbol max. unit note operating current t rc t rc (min), outputs open, one bank active i dd1 200 160 140 3 precharge standby current in power down mode t ck = 15ns, cke v il (max) i dd2p 3 3 3 precharge standby current in power down mode t ck = , cke v il (max) i dd2ps 3 3 3 precharge standby current in non-power down mode t ck = 15ns, cs# v ih (min), cke v ih input signals are changed every 2clks i dd2n 50 50 50 precharge standby current in non-power down mode t ck = , clk v il (max), cke v ih i dd2ns 30 30 30 active standby current in non-power down mode t ck = 15ns, cke v ih (min), cs# v ih (min) input signals are changed every 2clks i dd3n 60 60 60 active standby current in non-power down mode cke v ih (min), clk v il (max), t ck = i dd3ns 50 50 50 operating current (burst mode) t ck =t ck (min), outputs open, multi-bank interleave i dd4 240 200 170 3, 4 refresh current t rc t rc (min) i dd5 300 260 230 3 self refresh current cke 0.2v ; for other inputs v ih v dd - 0.2v, v il 0.2v i dd6 3 3 3 ma
etrontech em639325 rev. 2.1 20 aug. /2015 table 11. electrical char acteristics and recommended a.c. operating conditions (v dd = 3.3v ? 0.3v, t a = -40~85c) (note: 5~8) -5i -6i -7i symbol a.c. parameter min. max. min. max. min. max. unit note t rc row cycle time (same bank) 55 - 60 - 63 - t rcd ras# to cas# delay (same bank) 15 - 18 - 21 - t rp precharge to refresh / row activate command (same bank) 15 - 18 - 21 - t rrd row activate to row active delay (different banks) 10 - 12 - 14 - t ras row activate to precharge time (same bank) 40 100k 42 100k 42 100k ns t wr write recovery time 2 - 2 - 2 - t ccd cas# to cas# delay time 1 - 1 - 1 - t ck 9 cl* = 2 - - 10 - 10 - t ck clock cycle time cl* = 3 5 - 6 - 7 - t ch clock high time 2 - 2.5 - 2.5 - 10 t cl clock low time 2 - 2.5 - 2.5 - 10 cl* = 2 - - - 6 - 6.5 ns t ac access time from clk (positive edge) cl* = 3 - 5 - 5.4 - 5.4 t oh data output hold time 2 - 2.5 - 2.5 - 9 t lz data output low impedance 1 - 1 - 1 - t hz data output high impedance cl* = 3 - 5 - 5.4 - 5.4 8 t is data/address/control input set-up time 1.5 - 1.5 - 1.5 - ns 10 t ih data/address/control input hold time 0.8 - 0.8 - 0.8 - ns 10 t pde powerdown exit setup time t is+ t ck - t is+ t ck - t is+ t ck - ns t mrd mode register set command cycle time 2 - 2 - 2 - t ck t refi refresh interval time - 15.6 - 15.6 - 15.6 s t xsr exit self-refresh to any command t rc+ t is - t rc+ t is - t rc+ t is - ns *cl is cas latency. note: 1. stress greater than those listed under "absolut e maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . vih (max) = 4.6v for pulse width 3ns. vil(min) = -1.0v for pulse width 3ns. 3. these parameters depend on the cycle rate and t hese values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during every 2 t ck. 4. these parameters depend on the output loading. s pecified values are obtained with the output open. 5. power-up sequence is described in note 11. 6. a.c. test conditions
etrontech em639325 rev. 2.1 21 aug. /2015 table 12. lvttl interface reference level of output signals 1.4v / 1.4v output load reference to the under output load (b) input signal levels (v ih /v il ) 2.4v / 0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v output 1.2k ? 30pf 3.3v 870 ? output z0=50 ? 50 ? 30pf 1.4v figure 19.1 lvttl d.c. test load (a) figure 19.2 lvttl a.c. test load (b) 7. transition times are measured between v ih and v il . transition (rise and fall) of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit conditi on and are not at reference levels. 9. if clock rising time is longer than 1 ns, (t r / 2 -0.5) ns should be added to the parameter. 10. assumed input rise and fall time t t (t r & t f ) = 1 ns if t r or t f is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when cke= ?l?, dqm= ?h? and all input signals are held "nop" state. 2) start clock and maintain stable condition for minimum 200 s, then bring cke= ?h? and, it is recommended that dqm is held "high" (v dd levels) to ensure dq output is in high impedance. 3) all banks mu st be precharged. 4) mode register set command must be as serted to initialize the mode register. 5) a minimum of 2 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device. * the auto refresh command can be issue before or after mode register set command
etrontech em639325 rev. 2.1 22 aug. /2015 timing waveforms figure 20. ac parameters for write timing (burst length=4) t0 t1 t2 don?t care t ch activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t cl begin auto precharge bank b rax rbx ray rax cax rbx cbx ray cay ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 t rcd t rc t dal t wr write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a t is t is t ih t ih t is begin auto precharge bank a t is t ih hi-z clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em639325 rev. 2.1 23 aug. /2015 figure 21. ac parameters for read timing (burst length=2, cas# latency=3) hi-z clk cs# t0 t1 t2 cke don?t care ras# t ch cas# we# ba0,1 a10 a0-a9, a11 dqm dq activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t cl begin auto precharge bank b rax rbx rax cax rbx cbx ray ray ax0 ax1 t rrd t rc read command bank a activate command bank b read with auto precharge command bank b activate command bank a t is t ih t ih t is t is t ih t ras t rcd t ac t lz t hz bx0 bx1 t hz t rp precharge command bank a t oh
etrontech em639325 rev. 2.1 24 aug. /2015 figure 22. auto refresh (burst length=4, cas# latency=3) t0 t1 t2 don?t care precharge all command t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax cax rax ax0 t rp t rc auto refresh command auto refresh command activate command bank a read command bank a t rc t rcd clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em639325 rev. 2.1 25 aug. /2015 figure 23. power on seque nce and auto refresh hi-z t0 t1 t2 don?t care inputs must be stable for 200s t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t mrd mode register set command high level is reguired minimum for 2 refresh cycles are required t rp precharge all command 1st auto refresh (*) command 2nd auto refresh (*) command any command note (*) : the auto refresh command can be issue before or after mode register set command clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq address key
etrontech em639325 rev. 2.1 26 aug. /2015 figure 24. self refresh entry & exit cycle clk cs# t0 t1 t2 cke don?t care ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq self refresh entry t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 self refresh exit auto refresh t is hi-z t is t ih *note 1 *note 2 *note 3,4 t pde *note 5 *note 6 *note 7 t xsr *note 8 hi-z *note 9 note: to enter selfrefresh mode 1. cs#, ras# & cas# with cke shoul d be low at the same clock cycle. 2. after 1 clock cycle, all the i nputs including the system clock c an be don't care except for cke. 3. the device remains in selfrefresh mode as long as cke stays "low". 4. once the device enters selfrefresh mode, minimum t ras is required before exit from selfrefresh. to exit selfrefresh mode 5. system clock restart and be stable before returning cke high. 6. enable cke and cke should be set high for valid setup time and hold time. 7. cs# starts from high. 8. minimum t xsr is required after cke going hi gh to complete selfrefresh exit. 9. 4096 cycles of burst autore fresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst refresh.
etrontech em639325 rev. 2.1 27 aug. /2015 figure 25. clock suspension du ring burst read (using cke) (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a read command bank a ax0 ax1 ax2 ax3 t hz clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em639325 rev. 2.1 28 aug. /2015 figure 26. clock suspension du ring burst write (using cke) (burst length=4) hi-z t0 t1 t2 don?t care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a write command bank a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq dax0 dax1 dax2 dax3
etrontech em639325 rev. 2.1 29 aug. /2015 figure 27. power down m ode and clock suspension (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t is power down mode exit t pde power down mode entry read command bank a clock suspension start power down mode exit t ih rax rax cax ax2 ax0 ax3 active standby clock suspension end precharge command bank a power down mode entry precharge standby any command valid t hz clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq ax1
etrontech em639325 rev. 2.1 30 aug. /2015 figure 28. random column read (page within same bank) (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a raw raw cax aw0 aw1 ay2 precharge command bank a clk raz caw cay raz caz aw2 aw3 ax0 ax1 ay0 ay1 ay3 read command bank a read command bank a activate command bank a read command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em639325 rev. 2.1 31 aug. /2015 figure 29. random column wr ite (page within same bank) (burst length=4) hi-z t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank b rbw rbw cbx dbw0 dbw1 dby2 precharge command bank b clk rbz cbw cby rbz cbz dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby3 write command bank b write command bank b activate command bank b write command bank b cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq dbz0 dbz1
etrontech em639325 rev. 2.1 32 aug. /2015 figure 30. random row read (interleaving banks) (burst length=8, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank b rbx rbx rax bx0 bx1 ax0 precharge command bank b clk rby cbx cax rby cby bx2 bx3 bx4 bx5 bx6 bx7 ax1 activate command bank a read command bank a activate command bank b read command bank b cs# cke we# a10 ax6 ax7 high rax ax2 ax3 ax4 ax5 t rcd t ac t rp a0-a9, a11 dqm dq ba0,1 ras# cas# precharge command bank a by0
etrontech em639325 rev. 2.1 33 aug. /2015 figure 31. random row writ e (interleaving banks) (burst length=8) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbx dax3 dax4 dbx3 precharge command bank a clk ray cax cbx ray cay dax5 dax6 dax7 dbx0 dbx1 dbx2 dbx4 activate command bank b write command bank b activate command bank a write command bank a cs# cke we# a10 day1 day2 high rbx dbx5 dbx6 dbx7 day0 t rcd t rp a0-a9, a11 dqm dq ba0,1 ras# cas# precharge command bank b day3 t wr* t wr* dax0 dax1 dax2 *t wr >t wr (min.)
etrontech em639325 rev. 2.1 34 aug. /2015 figure 32. read and write cycle (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax day1 clk cax caz ax0 ax1 ax2 ax3 day0 write command bank a the write data is masked with a zero clock latency read command bank a the read data is masked with a two clock latency cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq az1 az3 cay day3 az0
etrontech em639325 rev. 2.1 35 aug. /2015 figure 33. interleaved column read cycle (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx ax0 ax1 bz0 precharge command bank b clk rbx cax cbx ax2 ax3 bx0 bx1 by0 by1 bz1 activate command bank b read command bank b precharge command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq cby cbz cay t rcd t ac read command bank b read command bank a ay2 ay0 ay1 ay3 read command bank b
etrontech em639325 rev. 2.1 36 aug. /2015 figure 34. interleaved column write cycle (burst length=4) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbw dax0 dax1 dby0 write command bank b clk rbw cax cbw dax2 dax3 dbw0 dbw1 dbx0 dbx1 dby1 activate command bank b write command bank b precharge command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq cbx cby cay t rcd write command bank b write command bank a dbz0 day0 day1 dbz1 write command bank b cbz t rrd >t rrd (min) t wr t wr dbz2 dbz3 precharge command bank b
etrontech em639325 rev. 2.1 37 aug. /2015 figure 35. auto precharge after read burst (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx bx2 rbx cax cbx ax0 ax1 ax2 ax3 bx0 bx1 bx3 activate command bank b read with auto precharge command bank a read with auto precharge command bank b cay activate command bank b ay2 ay0 ay1 ay3 read with auto precharge command bank b rby t rp begin auto precharge bank b begin auto precharge bank a rby cby by2 by0 by1 clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq high
etrontech em639325 rev. 2.1 38 aug. /2015 figure 36. auto precharge after write burst (burst length=4) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbx dbx2 rbx cax cbx dax0 dax1 dax2 dax3 dbx0 dbx1 dbx3 activate command bank b write with auto precharge command bank a write with auto precharge command bank b cay activate command bank b day2 day0 day1 day3 write with auto precharge command bank b rby t dal begin auto precharge bank b begin auto precharge bank a rby cby dby2 dby0 dby1 clk cs# cke we# ba0,1 a10 dqm dq high dby3 ras# cas# a0-a9, a11
etrontech em639325 rev. 2.1 39 aug. /2015 figure 37. full page read cycle (burst length=full page, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax ax+1 rbx cax rbx ax ax+1 ax+2 ax-2 ax-1 ax bx activate command bank b read command bank b precharge command bank b cbx burst stop command bx+3 bx+1 bx+2 bx+4 the burst counter wraps from the highest order page address back to zero during this time interval t rp rby rby bx+5 clk cs# cke we# a10 dq high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b ras# cas# ba0,1 a0-a9, a11 dqm
etrontech em639325 rev. 2.1 40 aug. /2015 figure 38. full page write cycle (burst length=full page) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax dax+1 rbx cax rbx dax dax+1 dax+2 dax+3 dax-1 dax dbx activate command bank b write command bank b precharge command bank b cbx burst stop command dbx+3 dbx+1 dbx+2 dbx+4 the burst counter wraps from the highest order page address back to zero during this time interval rby rby dbx+5 clk cs# cke we# a10 dq high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b ras# cas# ba0,1 a0-a9, a11 dqm data is ignored
etrontech em639325 rev. 2.1 41 aug. /2015 figure 39. byte read and write operation (burst length=4, cas# latency=3) t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax cax upper byte is masked write command bank a lower byte is masked cay read command bank a lower byte is masked caz clk cs# cke we# a10 dq n high lower byte is masked ras# cas# ba0, 1 a0-a9, a11 dqm m dqm n ax0 ax1 ax2 day1 day2 az1 az2 dq m ax1 ax2 ax3 day0 day3 day1 az0 az1 az2 az3 upper byte is masked note : m represent dq in the byte m; n represent dq in the byte n.
etrontech em639325 rev. 2.1 42 aug. /2015 figure 40. random row read (interleaving banks) (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command bank b rax cax by1 rbx rbx cay ax0 ax1 bx0 ay0 ay1 by0 by2 read command bank a read command bank b precharge command bank b (precharge temination) bz0 by3 bz1 read command bank a cbz t rp rbw rbw bz2 clk cs# cke ras# cas# we# a10 dqm dq rax cbx cby t rrd t rcd read command bank b read command bank b activate command bank b ba0, 1 a0-a9, a11
etrontech em639325 rev. 2.1 43 aug. /2015 figure 41. full page random column read (burst length=full page, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command bank b rax cax by1 rbx rbx cay ax0 ax1 bx0 ay0 ay1 by0 az0 read command bank a read command bank b precharge command bank b (precharge temination) caz read command bank a bz0 az1 az2 bz1 read command bank a cbz t rp rbw rbw bz2 clk cs# cke ras# cas# we# a10 dqm dq rax cbx cby t rrd t rcd read command bank b read command bank b activate command bank b ba0,1 a0-a9, a11
etrontech em639325 rev. 2.1 44 aug. /2015 figure 42. full page random column write (burst length=full page) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command bank b rax cax dby1 rbx rbx cay dax0 dax1 dbx0 day0 day1 dby0 daz0 write command bank a write command bank b precharge command bank b (precharge temination) caz write command bank a dbz0 daz1 daz2 dbz1 write command bank a cbz t rp rbw rbw dbz2 clk cs# cke ras# cas# we# a10 dqm dq rax cbx cby t rrd t rcd write command bank b write command bank b activate command bank b ba0,1 a0-a9, a11 t wr write data are masked
etrontech em639325 rev. 2.1 45 aug. /2015 figure 43. precharge te rmination of a burst (burst length=4, 8 or full page, cas# latency=3) t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax ay0 cax dax0 dax1 ay1 write command bank a activate command bank a activate command bank a ray precharge command bank a ay2 precharge command bank a cay t wr raz clk cs# cke we# a10 dqm dq high raz ray t rp read command bank a precharge termination of a read burst t rp precharge termination of a write burst write data are masked a0-a9, a11 ras# cas# ba0,1
etrontech em639325 rev. 2.1 46 aug. /2015 figure 44. 86 pin tsop ii packag e outline drawing information y 86 1 d e h e 0.254 ? l l 1 a a 1 a 2 s b e l l 1 c 43 44 symbol dimension in inch dimension in mm min normal max min normal max a ? ? 0.047 ? ? 1.20 a1 0.002 0.004 0.008 0.05 0.10 0.2 a2 0.035 0.039 0.043 0.9 1 1.1 b 0.007 0.009 0.011 0.17 0.22 0.27 c ? 0.005 ? ? 0.127 ? d 0.87 0.875 0.88 22.09 22.22 22.35 e 0.395 0.400 0.405 10.03 10.16 10.29 e ? 0.0197 ? ? 0.50 ? he 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 l1 ? 0.0315 ? ? 0.80 ? s ? 0.024 ? ? 0.61 ? y ? ? 0.004 ? ? 0.10 0 ? 8 0 ? 8 notes: 1. dimension d&e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. dimension s includes end flash. 4. controlling dimension: mm
etrontech em639325 rev. 2.1 47 aug. /2015 figure 45. 90 ball fbga 8x13x1.2mm(max. ) outline drawing information detail : "a" pin #1 top view bottom view side view dimension in inch dimension in mm symbol min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.012 0.014 0.016 0.30 0.35 0.40 a2 0.027 0.029 0.031 0.69 0.74 0.79 c 0.007 0.008 0.010 0.17 0.21 0.25 d 0.311 0.315 0.319 7.90 8.00 8.10 e 0.508 0.512 0.516 12.90 13.00 13.10 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.441 -- -- 11.2 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 f -- 0.126 -- -- 3.2 --

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